Battle commences in 50nm DRAM arena
Samsung and Hynix, two of the industry's DRAM leaders, have already begun migrating their production of major products to the 50nm class process node. Latest analysis on both 1Gbit DDR2 SDRAM parts from Samsung and Hynix revealed very interesting trends from the two Korean rivals.
The two 1Gbit DDR2 SDRAM devices that Semiconductor Insights (SI) has analyzed (Figure 1) are from the 50nm class process node. The analysis confirmed that the process node of the Samsung device is 58nm; SI confirmed this by measuring multiple wordline and bitline pitches using cross sections obtained via a scanning electron microscope. The same measurement techniques were used to determine the process node of the Hynix device as 54nm.
Despite the larger wordline and bitline pitch, Samsung's DRAM cell achieved smaller cell size by using a 6F²-based cell design. On the other hand, Hynix's 8F² cell design showed a 16.5 percent larger cell than Samsung's. It should be noted that despite the larger cell size, Hynix's 1Gbit DDR2 SDRAM achieved an impressive chip size of 45.1mm², only 2.7 percent larger than Samsung's 1Gbit DDR2 SDRAM. The floorplans for both devices look very similar; one exception includes Samsung design having two rows of pads in the central region; whereas, the Hynix design has all the pads aligned in one row.
In terms of DRAM cell and access transistor structure, the two rivals show very different approaches. As for Samsung's 58nm process technology, the cell design appears to have been changed from spherical-shaped recessed channel access transistor (S-RCAT) to RCAT. It appears that the tight pitch of 6F² cell design poses a challenge to design an S-RCAT-based cell. The Hynix's 54nm process technology maintains the same 8F²-based S-RCAT structure for the cell and the access transistor. To compensate for the change from S-RCAT to RCAT, Samsung appears to have made the RCAT recess deeper than that of Hynix's.
Another significant difference is the number of metal layers contained in Samsung's device. The Samsung 58nm 1Gbit DDR2 SDRAM device used only three levels of metallization; metal 1 is tungsten, whereas the remaining two metal layers are aluminum-based. This is a significant change given that Samsung managed to achieve a very competitive chip size with only three metal layers. Previous generations of DDR2 products from Samsung used four layers of metalization. Given the importance of cost reduction in the DRAM industry, combined with the recent steep decline in DRAM prices, Samsung's 58nm process technology with three metal layers is expected to achieve much needed production cost reduction, helping Samsung remain competitive in these tough market conditions.
|Samsung's DRAM cell achieved smaller cell size by using a 6F²-based cell design.|
Hynix's interconnect technology appears to be a traditional four-metal process—tungsten-based metal 1 and three aluminum-based metal 2, 3 and 4 layers have been confirmed by SI analysis.
After reviewing both companies' previous three generations of products, SI has revealed some interesting trends. Samsung introduced their 6F² cell-based 512Mbit DDR2 SDRAM at the 80nm process node. At the same process node, Hynix's 8F²-based cell was 33 percent larger than Samsung's 6F² cell. However, Hynix's design managed to compensate for the disadvantage of having a larger cell by achieving an impressive chip size with only 13 percent of the overhead against Samsung's design. Over the next two generations (60nm and 50nm class), Hynix pursued an aggressive scaling of their process node, reducing the die-size gap with Samsung. Hynix pushed 66nm when Samsung was using 68nm, and adopted the 54nm process node as opposed to Samsung's 58nm process node. These efforts have helped Hynix reduce the chip size gap with Samsung's counterpart product to less than 3 percent at 54nm process node, while maintaining an 8F² cell design.
It appears that the aggressive scaling effort, combined with some innovation in circuit and layout designs have helped Hynix maintain its competitiveness in the DRAM industry using 8F²-based cell technology.
We have also noted the difference in cell size overhead between Hynix's 8F² cells and Samsung's 6F²-based cells. As companies push the process technology forward, achieving smaller pitches for wordline and bitline, the 25 percent advantage of 6F²-based cell in a given process node is reduced.
At the 2007 Symposium on VLSI Technology, Samsung published a paper titled "Fully Integrated 56-nm DRAM Technology for 1-Gb DRAM." According to this paper, the 56nm process developed had 6F² cell with S-RCAT structure and four metal layers (one tungsten and three aluminum-based metal layers). This is in contrast with the production part that SI analyzed, which showed 6F² cell with RCAT structure and only three metal layers.
|Hynix's 8F² cell design showed a 16.5 percent larger cell than Samsung's.|
At this year's ISSCC 2009 program, Samsung presented another variant of their 50nm class process technology. A 56nm monolithic 4Gbit DDR3 with three metal layers (two copper and one aluminum) would be the first 4Gbit monolithic DDR3 and the first Samsung DRAM with copper interconnect technology. The larger chip size of 4Gbit density and higher performance requirement of DDR3 SDRAM would have required copper interconnect technology. Samsung appears to have managed to use only three metal layers in this challenging design.
Use of copper interconnect in DRAM is expected to accelerate into the 50nm class process node with the addition of Samsung and Elpida (which announced its 50nm DRAM with copper interconnect late 2008), as well as Micron, which has been using copper interconnect technology for several generations.
Another new technology being introduced to DRAM is 3D DDR3, using through-silicon via (TSV) technology. Samsung is expected to present their latest innovations in 8Gbit 3D DDR3 with TSV at ISSCC 2009.
This is a clear sign that DRAM manufacturers are constantly making improvements to their process technology, maintaining their competitive edge against their competitors. As the process node reaches the 50nm and 40nm class, there are some early signs of technical challenges. Uniform scaling in both the wordline and bitline direction from previous 80nm and 60nm process generations appears to be changing. Scaling in one direction is more challenging than in the other direction. Clear definition of 2F x 4F (8F² cell) or 2F x 3F (6F² cell) for DRAM cell dimension gets a little tricky in some cases. We also see that access-transistor design becomes more challenging due to the reduced size of the transistor and increased need for leakage control through better isolation.
The DRAM industry has many different choices to make: different cell designs; 6F² vs. 8F² and 6F² vs. 4F², the selection of interconnection material; aluminum vs. copper and the number of metal layers to used (three vs. four).
Some recent trends that reduce the number of interconnect layers show the emphasis on cost-reduction efforts in the DRAM industry. These different choices will pose challenges to some manufacturers with less favorable technologies. Competition between manufacturers with different technologies and approaches will become more evident—manufacturers will be required to develop competing technology or to come up with innovative alternative solutions to overcome the challenges. All aspects of these changes are important for the DRAM industry to remain a viable business.
- Young Choi
Senior Manager, Semiconductor Insights
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