Keeping the control ramp right

If the ramp driving your PWM-based controller isn't linear or monotonic, or just plain noisy, your DC/DC converter isn't going to work up to its capabilities. Here's what you need to know to get the best performance from your system.

Today's typical DC/DC power system relies on the slope of a ramp to set the duty cycle of a PWM controller. This is true for both voltage-mode controllers, which use a separately generated ramp for setting the pulse width; and current-mode controllers, which use a ramp generated by a current sensor monitoring the current in the switching element.

Fig. 1 shows a typical block diagram of a voltage-mode power controller, in this example the UC2823. A simplified schematic of the control circuit in a forward converter topology is shown in Fig. 2.

Fig.1: Typical PWM controller used for voltage-mode control

Let's examine this simplified ideal case for the ramp signal. We will ignore the voltage drops in diode D1 and the power MOSFET when they are conducting.

When the MOSFET power switch is turned on by the control circuit signal OUT, voltage VIN is applied across the primary winding of transformer T1. Thus voltage VTOUT appears at the secondary of T1. It's applied to output inductor LOUT through D1. This voltage is greater than the voltage on the output, VOUT. As a result, there's current buildup in LOUT.

When the power MOSFET turns off, the voltage on at the input of LOUT drops to zero. However, current is drawn through diode D2 and continues to flow through LOUT, though it decreases in a linear manner.

Fig.2: Simplified voltage-mode controlled converter

For this analysis we set the design parameters of a forward converter for an input-voltage range from 36-57V, and an output of 100W. The output voltage is set at 5V, and the switching frequency is 100kHz. We want to minimize the output ripple —no more than 50mV.

We size inductor LOUT for a peak-to-peak ripple current of 20 percent. We select the output capacitor so that half the output ripple is a function of the capacitance, and half is a function of the equivalent series resistance (ESR) of the capacitor.

The calculations for this design yield a transformer turns ratio of 11 to 2, an output inductor of 4.6 microhenries and an output capacitance of 400µF with a maximum ESR of 6.25m Ω. From this information, we can calculate the gain of the output filter as a function of the frequency (Fig 3).

Fig.3: Output filter gain

Next, investigate the control-to-output voltage gain of the power stage. To do this, we go to the UC2823's datasheet, which indicates a ramp on the Ct pin (oscillator) has a typical valley voltage of 1.0V and peak voltage of 2.8V. At the maximum input voltage, the duty cycle is 0.367 (calculated). At minimum input voltage, the duty cycle will be 0.859. When the circuit is in regulation, the ramp voltage switch point at maximum input voltage will be 1.66V, and 2.62V at minimum input voltage.

We can now determine the control-to-output gain at each of these input voltages and duty cycles by simply calculating the change in output voltage for the same input voltage from:

Vout = N D Vin

where VIN is the input voltage, N is the turns ratio (primary to secondary) and D is the duty cycle.

We calculate the corresponding change in the output voltage of the converter by changing the voltage at COMP by +100mV and finding the new duty cycle. From this, we calculate the new output voltage for each condition using the above formula. Determine the difference in the output voltage and divide the difference by 0.1V. This is the DC control-to-output gain.

Running through the calculations, we get a control-to-output gain of 7.576 at maximum input voltage. At minimum input voltage, we calculate the control-to-output gain as 5.596.

Linear ramp
Fig. 4 shows a diagram of a linear ramp and the four control (COMP) voltages for the duty cycle. The control voltages are arranged in sets of two; each set represents either a high or low input voltage (VIN minimum corresponds to V2, and VIN maximum corresponds to V1).

Fig. 4: PWM dynamics

The lower voltage in each voltage pair (V1 and V2) indicates the control voltage needed for a regulated output. The upper line indicates we have added 100 mV to the control voltage.

The actual change in the duty cycle (Δt) for each case is the same for each change in control voltage, but the change is a different ratio (change/previous time). In other words, a change of 100mV in the control voltage results in the same change in the duty cycle. However, at the maximum VIN, it is a much higher percentage of the duty cycle than at the minimum input voltage.

This different percentage change in duty cycle for the same variation in control voltage means that the control-to-output gain of the converter varies with input voltage, VIN (Fig. 5).

Fig.5: Control-to-output gain

Nonlinear ramp
Now let's look at the effect of having a nonlinear ramp. If the voltage for the ramp is generated by a resistor that charges a capacitor, and the peak voltage on the ramp is close to that of the source voltage used to generate the ramp, the ramp will have a pronounced curve. If this happens, and we use the same design except for the ramp shape, we will get a lower control-to-output gain for the condition where VIN is maximum. This is because the curved ramp is steeper, so the change in the pulse width for a fixed control voltage change will be less than for the linear ramp.

Fig.6: Curve ramp versus straight ramp

However, for the condition where VIN is at a minimum, the slope of the curved ramp at the low input voltage is much less steep (Fig. 6). So a change of 100mV in control voltage at the minimum input voltage will result in a significantly greater change in the pulse width. The change in pulse width is almost twice as large as for a straight ramp. Thus the control-to-output gain will be much higher for the nonlinear ramp than for the linear ramp. This suggests that with the correct shaping of the ramp, it's possible to get a flat gain across the entire input-voltage range.

Add some noise
Now let's look at a linear ramp with noise superimposed on it. Noise is dynamic and changes with the various pulse widths, so this example is illustrative only.

Fig. 7 shows a straight ramp with noise superimposed on it. Note the ramp's slope is not always monotonic, and in a noisy system this ramp can lead to problems. Thus we see the importance of ensuring that the converter control system is kept in a quiet area of the circuit board with appropriate noise reduction methods employed throughout.

Fig.7: Effects of noise on the ramp

Noting that the noise is not monotonically increasing, we see that the pulse width needed for both minimum input voltage and maximum input voltage for the circuit in Fig. 2 cannot be achieved because the voltages needed to generate the desired duty cycles are at points A1 and A2 on the ramp. They are preceded by a voltage that is higher because the ramp is decreasing immediately preceding the desired duty cycle.

If the COMP voltage was at the level needed to generate the previous case duty cycle, it would be tripped at points B1 and B2—before the desired pulse width was reached. This is because the ramp voltage is higher than the voltage at COMP before that point, and the comparator would trip on the first point it encounters.

If the voltage at COMP increases slightly, the pulse width takes a step function to C1 or C2, depending on the value of VIN—both of which are larger values than would be present with a linear ramp. In the end, the COMP voltage makes small changes back and forth, resulting in large changes in duty cycle. This very large jump in duty cycle for very small change in control voltage is the equivalent to an infinite control-to-output gain over a small dynamic area of the control loop's operating range.

If the voltage at COMP were coincident with a point that was almost flat, but still slightly ascending, the result would be a very high linear gain. If the ramp was truly flat, the dynamic gain at that point would be infinite. This condition leads to stability problems in the converter.

In summary
The design of the ramp is one of the key functions in the control-to-output gain of a PWM converter. The control-to-output gain changes as the input voltage changes. This effect in part is due to the relative position of the control voltage on the ramp.

The designer should also be aware of the effects that the ramp shape will have on the control-to-output gain of the converter. The flatter the ramp, the higher the control-to-output gain.

The ramp peak-to-peak voltage should be as large as is practical to keep the signal-to-noise ratio (SNR) high. Noise on the ramp can cause jitter or oscillations. Thus, it is important to keep the control circuit away from the noise sources and provide a quiet environment.

One of the best ways to do this is to have the control circuit on a separate ground with a single point contact to the power ground plane. Having a single-point contact (ideally, also the ground-point of the control IC) will limit the circulating ground currents, which are potential noise sources.

Keywords: ramp control   PWM   DC/DC converter