Reap the rewards of package-aware design
Author:Jayshree Desai
Chip designers must consider package routability, power delivery and I/O behavior during the initial I/O planning process. To do so, they should combine package-aware I/O planning with automated floor-plan synthesis, which can be very cost-effective for the chip floor plan and the package layout.
Please login to view article>>
Registered already? Login to view complete content.
If you have already registered on the following websites, please log in using your email address and password
eeForum: Demystifying Vietnam What does Vietnam offer that a rising number of top-tier semiconductor companies are setting up and expanding operations there?