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'Openness' fulfills SystemVerilog promise

Posted: 01 Apr 2008  Print Version  Bookmark and Share

Keywords:openness  open SystemVerilog  Open Verification Methodology 

Krolikoski: OVM is a truly open SystemVerilog class library and methodology package that can be used free of any restraints imposed by either Cadence or Mentor.

One of the ploys of many an EDA company releasing a technology is to call the technology "open." Unfortunately, "openness" is an imprecisely defined term, and much technology touted as "open" is all too often encumbered by legal requirements impeding its truly open use.

But that's not the case with the recent release of Cadence's and Mentor Graphics' "Open Verification Methodology" (OVM). OVM is a truly open SystemVerilog class library and methodology package that can be used free of any restraints imposed by either Cadence or Mentor. This true openness will dramatically help in fulfilling the original promise of SystemVerilog.

Consider the case of an EDA startup armed with an idea that could potentially revolutionize functional verification. Because it uses OVM, the startup doesn't need to reinvent the SystemVerilog wheel, but can instead use OVM as a product enabler without any restrictions. This facilitates the introduction of new EDA technology and is clearly a win for the entire industry, allowing verification startups to focus on their "secret sauce."

OVM allows fine-tuning vendor-provided OVM class libraries and methodologies to meet specific requirements. By using OVM, the company will be able to internally and externally distribute the source code resulting from this fine-tuning, a solution that incorporates a robust commercial product that can be freely extended and redistributed to solve evolving design and verification issues.

User-company executives reticent to depend on a single EDA vendor will be glad to find that OVM provides seamless interoperability between the IEEE 1800 SystemVerilog supporting platforms of two of the three major EDA vendors. These executives will no longer be forced to make the choice between three incompatible sets of base class libraries and methodologies, but can now choose a solution supported by two thirds of the simulation seats worldwide.

Sharp contrast
The openness of OVM contrasts sharply with the closed nature of its competition in the SystemVerilog methodology area. A look at the competition's license under "Other rights and restrictions" will reveal no rights granted; instead three clauses begin with the words "You may not�" and are followed by a fourth clause admonishing licensees that their licenses will be summarily terminated if any of the preceding conditions are violated. This is exactly the sort of anti-openness that has kept SystemVerilog from fulfilling its original promise.

On the other hand, the Apache 2.0 license, under which OVM is registered, mentions termination only in reference to cases in which one licensee institutes patent infringement proceedings against another licensee. In other words, license termination is invoked only when any licensee attempts to restrict the terms of the license. In all other cases, licensees of OVM may use the product however they wish without reporting to either Mentor or Cadence, so long as all copyright notices are maintained and all derivative works are distributed under the same open license.

Will the introduction of this robust, interoperable SystemVerilog solution help fulfill that language's original promise?

The case is open-and-shut.

- Stan Krolikoski
Group Director, Standards and Interoperability
Cadence Design Systems Inc.





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