Enhanced HSPICE revs up circuit simulation
Synopsys Inc. has unveiled improvements to its HSPICE core engine technology that boost performance for analog and mixed-signal designs. In addition, new multithreading capabilities in the latest release of the HSPICE simulator speed up circuit simulation by taking advantage of multicore computer architectures. As a result, circuit designers can now run HSPICE post-layout simulations up to three times faster on single-core processors and up to six times faster on four-core processors.
"Implementing mixed-signal security processor designs in smaller geometries necessitates accurate transistor-level simulation with post-layout parasitics," said Jeff Berkman, chief technology officer at Priva Technologies Inc., a company that develops and markets advanced hardware- and software-based authentication and security platforms for the travel, financial, retail, government and enterprise markets. "With post-layout parasitic data growing exponentially, having a fast simulation tool that can also take advantage of our investment in a multicore compute platform is critical to the success of our circuit designs. We rely on Synopsys to deliver both the simulation technology enhancements and multicore platform support required to increase our productivity and accelerate time-to-results."
The newest version of the HSPICE simulator delivers improvements in the symbolic DC operating point convergence algorithm, transient time-step control, netlist parsing and model performance. These enhancements accelerate overall simulation throughput on single-core computers.
Previously, HSPICE multithreading capabilities allowed circuit designers to quickly simulate large pre-layout designs. With the March 2008 release, Synopsys has extended HSPICE multithreading capabilities to enable simulation of large post-layout designs containing in excess of a million resistive and capacitive parasitic effects. As a result of these enhanced multithreading simulation capabilities, fully extracted post-layout designs can now be simulated in just hours instead of days.
In a related announcement, Synopsys launched its multicore initiative to assist IC design companies in maximizing the throughput of their multicore compute infrastructure to reduce time-to-results (TTR).
"Synopsys is deploying comprehensive support for multicore processing across its core EDA and design-for-manufacturability product portfolios. The HSPICE circuit simulator is one of the first technologies to benefit from this effort," said Bijan Kiani, VP of product marketing at Synopsys. "Full multithreading capability in HSPICE enables designers to take advantage of their investment in a multicore compute infrastructure and attain signoff-quality post-layout simulation results in a fraction of the time it takes with other simulators."
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