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[ Jul 5, 2008 ]

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Hardware acceleration of 3GPP turbo encoder/decoder BER measurements using system generator

This application note describes how a hardware implementation of the Xilinx 3GPP Turbo encoder and decoder cores is incorporated into a system generator design to provide BER performance measurements. Within the hardware design, a noisy channel model is used to test the encoder/decoder combination under a variety of Additive White Gaussian Noise (AWGN) conditions. A combination of Simulink blocks and MATLAB scripts is used to control the hardware and collect and display the results with a minimum of user interaction.

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