Reference system: MCH OPB DDR SDRAM with OPB Central DMA
Author: Casey Cain
This application note describes how to set up MicroBlaze parameters for caching, the clocking structure for the MCH OPB DDR SDRAM, and parameters for OPB burst transactions from the OPB Central DMA controller. This reference system is targeted for the Xilinx SP305 Spartan-3 development board.
Please login or register with us to view this article>>
Registered already? Login to view complete content.
If you have already registered on the following websites, please log in using your email address and password
eeForum: Demystifying Vietnam What does Vietnam offer that a rising number of top-tier semiconductor companies are setting up and expanding operations there?
|
|
|
|
|Electronic Components|Computer Products|Trade Show Center
|Site Feedback|Site Map|Help|About Us|Contact Us|Terms of Use|Privacy Policy|Security Commitment
