PowerPC processor with floating point unit for Virtex-4 FX devices
Author: Gaurav Gupta, Ben Jones, Glenn C. Steiner

This application note describes how to implement a Virtex-4 FX PowerPC 405 system with the Xilinx floating point unit (FPU) coprocessor. An FPU connected to the PowerPC auxiliary processor unit (APU) interface can accelerate software applications from anywhere between three to twenty times. The reference design provided includes a completed design created using the Xilinx Embedded Development Kit (EDK). Source code for a finite impulse response (FIR) filter is provided along with a graphics utility for display output on a Windows-based PC.