DDR SDRAM controller using Virtex-4 FPGAs
Author: Rich Chiu

This application note describes a DDR SDRAM controller implemented in a Virtex-4 XC4VLX25 FF668 -10C device. This implementation uses direct clocking for data capture and an automatic calibration circuit to adjust delay on the data lines. DDR SDRAM devices are low-cost, high-density storage resources that are widely available from many memory vendors. This reference design has been developed using both SDRAM components and DIMMs.