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[ Jul 6, 2008 ]

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Synthesizable CIO DDR RLDRAM II controller for Virtex-4 FPGAs

This application note describes how to use a Virtex-4 device to interface to Common I/O (CIO) Double Data Rate (DDR) Reduced Latency DRAM (RLDRAM II) devices. The reference design targets two CIO DDR RLDRAM II devices at a clock rate of 200/235MHz with data transfers at 400/470Mbps per pin.

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