For Registered Users Home / For Registered Users

Clock implementation tool supports 65nm design flows


Azuro said version 3 of the PowerCentric clock implementation solution provides 15 percent to 25 percent power reduction to support advanced variability-aware design flows at 65nm and below.

Please login to view article>>

Email address:
Password: Password is case-sensitive.
Remember password Forgot your password?
 
If you have already registered on the following websites, please log in using your email address and password

EE Times-Asia sites:

Latest News
Talkback

eeForum:
Demystifying Vietnam

What does Vietnam offer that a rising number of top-tier semiconductor companies are setting up and expanding operations there?

more

 
Top tech resources
 
India Newsletter

1.Board design becomes a nimble giant

2.ECAD-MCAD needs unified solution

3.Smart optical nets power enterprise

4.Fibre-optic networking

 
Go to top