Structured ASIC devices embed PCI Express physical layer
There are 12 devices in the CX6100 family with densities ranging from 240K to 1.8M ASIC gates, up to 1.1Mb of embedded SRAM and maximum operating frequencies of up to 250MHz across the die. Four on-chip, configurable, low-jitter PLLs support output frequencies from 10MHz to 1GHz.
The CX6100 structured ASIC family features an embedded PCI Express physical layer (PHY). The devices have a generic fabric that consists of gates and programmable I/Os, and a few fast PLLs that its customers can use, but what sets this design apart is there is a complete PCIe subsystem.
"What we've done is taken care of integrating the whole subsystem for the customer," said Wouter Suverkropp, director of marketing at ChipX. "We've taken our core fabric and added to it a PCIe PHY, an optional PCIe controller and some verification solutions. The entire solution comes from us, which is part of the value—it all works together."
There are several challenges associated with designing a standard cell with an internal PCIe PHY. In typical PCIe system solutions, the analog and digital components as well as smart circuitry are pieced together from different vendors. In addition, the design cycle of the chip is longer than a standard cycle of PCIe, which could pose a problem. By the time the device hits the market, it could be outdated, he said.
Also, if a designer builds a chip with an internal PHY, it has to be characterized and determined that it complies with PCI rules. Not only does that require expensive lab equipment, it's a tricky thing to do, he said.
"Designing the chip package is hard to do with high data rates. You get highly a highly integrated solution with low latency and buffers, which is for a smaller design overall," he added.
When using an FPGA with an external PHY, the designer is limited to only one lane only. As a result, an enormous amount of signals must be transported between the PHY and FPGA, typically between 34 and 220 signals. The high-speed signals require a high- speed grade FPGA, which is very power hungry. An FPGA with a built-in PHY also only has one lane and is not PCIe compliant even though it can be upgraded to the PCIe speed of 2.5Gbps.
The PCIe controller is a piece of synthesizable IP. It gets implemented in the core fabric of the CX6200 product and the customer hands off the design to ChipX. It is very configurable, enabling the designer to use it with 1, 4 or 8 lanes, up to 8 virtual channels and up to six base address registers.
With the optional PCIe 1.0a compliant controller, designers can develop root port, bridge and end-point designs. It is designed to handles the full 4KB payload size. It supports all the power-management states, and offers lane reversal, a trick designers appreciate because it makes port layouts much easier. The controller is PCI-SIG compliance-tested.
"The fact that individual components of a solution have fast compliance adds confidence to customers, so that when they go for compliance testing with their final product, they are going to pass it. This is a big deal because if they don't pass compliance testing, they cannot launch their product," he said.
The second component is the PHY analog interface that sits between the logic on the chip and the outside, like the cable or board. Analog has to be custom in every chip; by ChipX implementing it in core fabric, the customer no longer has to worry about that. They have a built-in connection to the outside of the chip with a PIPE interface. It also offers complete PIPE interoperability for customers that want to use their own PCIe controller.
The PHY has a random loop back test. It can also autocalibrate and change the pre-emphasis. "What that boils down to is higher signal quality, which means higher throughput and more bits per second," he said.
Tested prototypes can be received in four weeks. Pricing for the CX6100 devices starts at less than $7 in 100,000-unit volumes.
- Ismini Scouras
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