Dynamically reconfigurable SoC supports 'silicon-sharing'

Atmel Corp. has launched what it calls the industry's first family of dynamically reconfigurable systems-on-chips (SoCs) that allows multiple interfaces, peripherals and/or operators to share the same silicon at different times.

The FPSLIC II (Field Programmable System Level IC) is a dynamically reconfigurable programmable SoC that integrates Atmel's 40 MIPS, 8bit AVR processor, with 36KB program/data SRAM, a hardware multiplier, peripherals and a dynamically reconfigurable FPGA, with 256 to 2,300 core cells. A single piece of silicon can implement multiple, interchangeable peripherals, computational operators, and bus interfaces, including SDIO, PCI, PCMCIA, HDLC, and Ethernet, according to Atmel.

Silicon sharing is said to be extremely important in power- and space-constrained systems, such as new generation cell phones, PDAs, notebook computers, and printer/fax machines. Increasingly these devices must perform multiple functions (e.g. camera, MP3 player, phone) without sacrificing battery life, product size or product cost.

FPSLIC II power consumption is 50µA in standby and 2mA/MHz to 3mA/MHz during operation. With a 4MHz clock, the 8bit, hardware-accelerated FPSLICii and external memory consumes 9.2mA and can execute the same functions as a 200MHz 32bit RISC processor with four times the power drain. Using an FPGA without silicon-sharing would require a 200,000 gate device with power drain of 300mA. This is 32 times the power consumption of FPSLIC II, said the company.

FPSLIC II's silicon-sharing capability is enhanced by Atmel's back-end EDA tools—Reconfiguration Designer and Temporal Designer. The tools are the first to automate the implementation, timing, and control of the silicon-sharing process, according to Atmel. Previously, the design of silicon-sharing systems was essentially impossible because, even though many FPGAs can be reconfigured during operation, there have been no tools to automate reconfiguration control and timing.

The main obstacles to silicon-sharing have always been ensuring that the correct functionality is loaded into the FPGA at the correct time and that functions are not loaded on top of each other. Since either of these can cause catastrophic system failure, adding new features has typically required the addition of dedicated silicon (i.e. a larger FPGA), increasing both power consumption and system cost. Atmel has solved this problem by placing a configuration controller, two DMA controllers, a dedicated FPGA-to-AVR interface and a "virtual socket" in the FPGA portion of the programmable SoC. The "virtual socket" is populated from a library of previously designed peripherals, interfaces or operators that share the same silicon.

Atmel provides a library of reference designs for interfaces, peripherals and hardware accelerators that includes Ethernet, memory, SPI, SDIO, multimedia card, DMA, speech synthesis, ADPCM, audio codec interfaces, and DES/triple DES encryption algorithms. The company will introduce a library of pre-routed "drag-and-drop" co-processors and interfaces later this year. Designers may also use the company's System Designer EDA tool to develop custom IP for silicon sharing.

The on-chip AVR and reconfiguration controller manage the reconfiguration process. Based on inputs to the Reconfiguration Designer tool, the configuration controller signals the AVR when it is time to reconfigure the virtual socket, which IP block to load, the number of cycles required for execution and other constraints. At the time the design is done, System Designer checks that all the required library elements exist, places and routes the design, and generates appropriate bitstreams for the entire hardware design, including the virtual socket for the reconfigurable elements.

The reconfigurable elements (peripherals, interfaces, etc.) are individually placed and routed to fit the virtual socket. System Designer then assembles all bitstreams into a "master" bitstream, with memory pointers, that is stored in external memory.

FPSLIC II's virtual socket can be reconfigured at any time during system operation from a library of pre-compiled IP cores stored in external flash memory. At 15MHz, reconfiguration takes less than 15ms.

FPSLIC II family devices are available now, with FPGA densities of from 256 to 2,300 core cells, in Pb-free 144-pin TQFP and 256BGA packages. Prices are as follows in quantities of 10,000 units: the AT94S05AL-25BQU 256 core cells at $5, the AT94S10AL-25BQU 512 core cells at $10, and the AT94S40AL-15DGU 2300 core cells at $15.

- Marty Gold

eeProductCenter

Keywords: atmel   systems-on-chip   soc   fpslic ii   field programmable system level ic