ST to use Rambus Fiber Channel, PCI Express apps
The Rambus family of RaSer cells offers designers scalable serial link architectures that are optimized to address current and future serial link applications requiring the highest bandwidth and channel count on a single chip. The RaSer serial link family includes a variety of backplane serial interfaces, Gigabit and 10-Gigabit Ethernet PHYs, XAUI and double-XAUI serial interfaces, PCI Express and Turbo PCI Express PHYs, 1, 2 & 4 Gbps Fibre Channel and SONET/SDH 2.5Gbps PHYs, and 5-12.5Gbps high-speed serial interfaces. These solutions currently support all major foundry processes ranging from 180nm to 65nm.
Kevin Donnelly, VP of engineering at Rambus, stated "The growing trend of outsourcing serial link technology dramatically reduces an ASIC supplier's development costs and provides its customers fast access to silicon-proven solutions for all the latest interface standards. The benefit to ST's customers includes faster time to production, resulting in an ability to increase market share with their next-generation products."