For Registered Users Home / For Registered Users

Physical design flow taps partition layout
Author: Arun Balakrishnan, Wolfgang Roethig, Gopal Dandu, Benny Winefeld

This article describes a new hierarchical design flow and its usage on a 3 million-gate chip.

Please login or register with us to view this article>>


If you have already registered on the following websites, please log in using your email address and password

EE Times-Asia sites:

Latest News
Talkback

eeForum:
Demystifying Vietnam

What does Vietnam offer that a rising number of top-tier semiconductor companies are setting up and expanding operations there?

more

 
Top tech resources
 
Go to top