For Registered Users Home / For Registered Users

Memory verification needs fresh approach
Author: K. C. Chen

By interpreting parameter values corresponding to the implementation structure, equivalence-checking comparisons between RT and transistor level can be easily accomplished.

Please login or register with us to view this article>>


If you have already registered on the following websites, please log in using your email address and password

EE Times-Asia sites:

Latest News
Talkback

eeForum:
Demystifying Vietnam

What does Vietnam offer that a rising number of top-tier semiconductor companies are setting up and expanding operations there?

more

 
Top tech resources
 
Go to top