Home | Login | Register Now   [Jan 08,2009]
Global Sources
EE Times-Asia
For Registered Users Home / For Registered Users

An improved PLL design method without natural frequency and damping
Author: Morris Smith

This application note presents a design guide for PLL synthesizers used in wireless products. It focuses on compact, low current and low cost synthesizers, without considering the calculations for natural frequency and damping.

Please login or register with us to view this article>>


If you have already registered on the following websites, please log in using your email address and password

EE Times-Asia sites:

Latest News
Talkback

eeForum:
Demystifying Vietnam

What does Vietnam offer that a rising number of top-tier semiconductor companies are setting up and expanding operations there?

more

 
Top tech resources
 
India Newsletter
 
Go to top