For Registered Users Home / For Registered Users

Estimating IC power consumption at the RT Level
Author:Sheng Deng

Chip complexity raises the power consumption of a device to unprecedented levels. In this light, moving power analysis to the front end of the design flow enables you to make critical power-saving decisions early on and avoids costly, time-consuming iterations through synthesis and gate-level analysis.

Please login to view article>>

Email address:
Password: Password is case-sensitive.
Remember password Forgot your password?
 
If you have already registered on the following websites, please log in using your email address and password

EE Times-Asia sites:

Latest News
Talkback

eeForum:
Demystifying Vietnam

What does Vietnam offer that a rising number of top-tier semiconductor companies are setting up and expanding operations there?

more

 
Top tech resources
 
India Newsletter

1.Board design becomes a nimble giant

2.ECAD-MCAD needs unified solution

3.Smart optical nets power enterprise

4.Fibre-optic networking

 
Go to top